The present invention is in the field of integrated circuit networks and more particularly is directed to charge domain parallel processing networks.
In the prior art, multiplier circuits have generally been provided by signal transformations in the current domain, i.e. by controlling sums of weighted current signals.
In one form, multiplying digital-to-analog converter devices have been produced using bucket brigade devices (BBD's). These converter devices generally utilize a set of binary-weighted capacitors which have an analog signal impressed across them. MOS transistors drive currents into and out of selected ones of the set of capacitors. The particular ones of the set of capacitors which are so driven is controlled by gates which are controlled by a digital word signal (which may be user controlled for a variable multiplier, or may be preset for a fixed weight multiplier). The charging or discharging currents for the capacitors are summed and serve to launch a charge packet in a BBD. While that resultant charge packet in the BBD is proportional to the product of a digital word (which controls the gates to the respective capacitors) and an analog voltage applied to those capacitors, the generation of this charge packet is relatively slow, principally due to the long time constant associated with the MOS transistors used in the charging of the capacitors.
It is an object of the present invention to provide a charge domain parallel processing network.
It is another object to provide a charge domain vector-matrix product network.
Yet another object is to provide a charge domain matrix-matrix product network.
Still another object is to provide a charge domain triple matrix product device.